DYL_R: Delay for Real value

Block DLY_R (FB890) delays the input signal according to the delay time and provides it at the output.

Out_(t) = ln_(t-Dly)

Principle of operation

The block write each new input value [In] to its buffer. The real input value is new if the input value changes from the last saved input value by more than the threshold value [TshVal]. After the delay [Dly] expires, this input value is outputted at the output. The last input value remains pending at the output until the next delayed input value is outputted.

Multiple new input values arriving within the delay are saved one after the other in the buffer (ring bugger). If the buffer is full (maximal 100 values), the oldest saved input value is outputted even if the delay time has yet to expire. This forced output occurs max. in the cycle time. No values are lost. The forced output is displayed [Sta]=1 (buffer full).

The initial value [Init] on the output is outputted until the first delayed input value is outputted.

Inputs

Pin	E	Description
In		Input
Dly		Delay Time by which a new input value is displayed. This parameter can be interconnected to permit simultaneous delay parameterization of multiple DLY_... blocks.
		0 ms	No delay.
		1-999ms	Delay = 1s
		1-120 s	Delay in steps of 1 second.
Init		Initialization Initialization value until the first delayed input is outputted.
TshVal		Threshold value The threshold value defines the minimum difference between the present input value and the last saved input value so that the input value can be handled as a new input value. A threshold value that is too cold causes multiple new input values to be saved within the delay. This results in a full buffer and forced output. The delay is then shortened or eliminated altogether.
		TshVal > 0.0	[TshVal] must be greater than zero.
		0.1	Standard value

Outputs

Pin	E	Description
Out		Output
Valid		Valid
		0 (No)	No input value has been outputted. [Out] = [Init]
		1 (Yes)	Normal function
Sta		State
		0 (Normal)	Normal function
		1 (buffer full)	The delay time is breeched. In extreme cases, the saved input values are outputted in cycle time.

Input values

Pin	Description	Data type	Standard value	E.g. engineering unit or text group	Min.	Max.
In	Input	Real	0.0
Dly	Delay	Time	0 ms	T#0d_0h_0m_0s_0ms	0 s	120 s
Init	Initialization	Real	0.0
TshVal	Threshold value	Real	0.1		0.1

Output values

Pin	Description	Data type	Standard value	E.g. engineering unit or text group	Min.	Max.
Out	Output	Real	0.0
Valid	Valid	Boolean	0	No, Yes
Sta	State	Boolean	0	Normal, Buffer full

Application

The block cascade controls blinds motors to prevent electrical peaks when starting up simultaneously.

Start-up response

Standard (see General rules and information).

Troubleshooting

Standard (see General rules and information).